1. Field of the Invention
The present invention relates to thin-film field-effect transistors, and more particularly to a method of fabricating devices which aligns source/drain (S/D) contacts with a gate electrode, and utilizes a single lithographic step to minimize the time and cost of producing such a self-aligned device.
2. Description of the Related Art
In a conventional staggered inverted bottom-gate thin-film transistor (TFT), such as those used in active matrix displays, the source and drain electrodes of all TFTs are aligned globally using corner alignment marks on a surface. The use of alignment marks leads to offsets in positions underlying gate electrodes and source and drain contacts electrodes. Because the S/D contacts are not self-aligned, the degree of overlap is usually increased at the mask level to allow for these offsets. This is undesirable because it increases the source-drain to gate (S/Dxe2x88x92G) capacitance of the devices, which in turn increases the pixel feedthrough voltage (xcex94Vp) in the active matrix display.
The feedthrough voltage is caused by charge stored in the TFT S-G capacitance (Cgs) when the pixel TFT has charged the pixel and returns to its OFF state. The xcex94Vp offset must be compensated for using a combination of passive elements (storage capacitors) included in the active matrix design and suitable electronic drive schemes. Any shift in S/D alignment across the active matrix may lead to incomplete compensation of xcex94Vp, and hence to visual artifacts in the finished display.
Therefore, a need exists to produce TFTs with self-aligned S/D contacts to reduce or eliminate the problems outlined above. In addition to reducing S/Dxe2x88x92G capacitance and increasing pixel charging uniformity, it is also desirable to produce a TFT with a shorter channel since less total S/D overlap is should be reduced. A shorter channel results in more current drive available for pixel charging and hence a shorter charging time which is important for high-resolution, high-performance active matrix displays.
A method, in accordance with the invention, for forming a thin film transistor having source and drain electrodes self-aligned to a gate electrode by employing a single lithographic step includes forming an opaque gate electrode on a substrate, depositing a first dielectric layer on the gate electrode and the substrate, depositing a semiconductor layer on the first dielectric layer, and depositing a second dielectric layer on the semiconductor layer. A first photoresist is deposited on the second dielectric layer and patterned by employing the gate electrode as a mask for blocking light used to expose the first photoresist. The second dielectric layer is etched to form a top insulator portion of the second dielectric layer in alignment with the gate electrode. The first photoresist is removed. A doped semiconductor layer and a conductive layer are deposited. A second photoresist is formed on the conductive layer. The second photoresist is patterned to form component patterns and to form a contiguous transistor electrode pattern covering the top insulator portion. Non-selectively etching the second photoresist and the conductive layer, a gap is formed in the second photoresist for the transistor electrode pattern at the top insulator portion. The conductive layer and the doped semiconductor layer are etched selective to the second photoresist such that a source electrode and a drain electrode are formed which are self-aligned relative to the gate electrode.
Another method, in accordance with the invention, for forming a thin film transistor for an active matrix liquid crystal display having source and drain electrodes self-aligned to a gate electrode by employing a single lithographic step includes forming an opaque gate conductor layer on a substrate. The gate conductor layer has gate electrodes. A first dielectric layer is deposited on the gate conductor layer, on the gate electrodes and on the substrate, and a semiconductor layer is deposited on the first dielectric layer. A second dielectric layer is deposited on the semiconductor layer, and a first photoresist is deposited on the second dielectric layer. The first photoresist is patterned by employing the gate electrodes as a mask for blocking light used to expose the first photoresist. The second dielectric layer is etched to form a top insulator portion of the second dielectric layer in alignment with each of the gate electrodes. The first photoresist is then removed. A doped semiconductor layer is deposited on the top insulator and the semiconductor layer, and a conductive layer is deposited on the doped semiconductor layer. A second photoresist is formed on the conductive layer, and the second photoresist forms a non-planar surface due to a height of the top insulator portion. The second photoresist is patterned for pixel components and forms a contiguous transistor electrode pattern covering the top insulator portion. The second photoresist and the conductive layer are non-selectively etched to form a gap in the second photoresist for the transistor electrode pattern at the top insulator portion. The second photoresist is removed from the top insulator portion such that a sufficient thickness of the second photoresist pattern remains to provide for etching of the conductive and doped semiconductor layers. The conductive layer and the doped semiconductor layer are etched selective to the second photoresist such that a source electrode and a drain electrode are formed which are self-aligned relative to the gate electrode. The second photoresist is removed.
In other methods, the step of non-selectively etching the second photoresist may include the step of plasma ashing the second photoresist and the conductive layer to form the gap in the second photoresist at the top insulator portion. The step of plasma ashing the second photoresist may include employing oxygen plasma. The conductive layer may include at least one of aluminum, molybdenum, chromium, tungsten and copper, and the step of etching the conductive layer may include the step of wet etching the conductive layer and the doped semiconductor layer with a mixture of phosphoric, acetic and nitric acids. The conductive layer may include at least one of Indium Tin Oxide and Indium Zinc Oxide. The step of patterning the second photoresist layer to form patterns for pixel components may include the step of patterning the second photoresist layer to form patterns for at least one of data lines and capacitor electrodes. The steps of forming the top insulator portion with tapered edges and forming the gate electrode with tapered edges may be included. The thin film transistor may include a length between about 2 microns to about 10 microns.